2009-08-24

tracemonkeyのデバッグ方法が変わっていた

tracemonkeyを最近いじることがなかったんだけど、久々に触ってみたところ、デバッグ方法が変更になってた。

従来は、

TRACEMONKEY=verbose

と環境変数を設定すればよかったんだけど、今は、TMFLAGSにいろいろ設定するらしい。例えば、こんな感じ。

TMFLAGS=liveness,assembly

で、このように設定すると、

js> var a = 0; for(i=0;i<100;i++) a=a+i;

nanojitは、LIRのコードを生成するので、以下のログを吐く

================================================================================
=== BEGIN LIR::compile(000000000054A470, 0000000000561FC0)
===

=== Results of liveness analysis:
===
  Live instruction count 33, total 53, max pressure 7
  Side exits 1
  Showing LIR instructions with live-after variables

  state = iparam 0 rcx           state
  sp = ldq state[0]              state sp
  rp = ldq state[8]              state sp rp
  cx = ldq state[16]             cx state sp
  eos = ldq state[24]            cx eos state sp
  eor = ldq state[32]            cx eor state sp
  ld1 = ld cx[0]                 cx state ld1 sp
  ld2 = ld state[816]            cx state ld2 sp
  sti sp[0] = ld2                cx state ld2 sp
  ldq1 = ldq cx[296]             cx ldq1 state ld2 sp
  ldq2 = ldq ldq1[120]           cx ldq2 state ld2 sp
  map = ldq ldq2[0]              cx state map ld2 sp
  ld3 = ld state[824]            cx state ld2 sp ld3
  sti sp[8] = ld3                cx state ld2 sp ld3
  add1 = add ld2, ld3            cx add1 state sp ld3
  sti sp[0] = add1               cx add1 state sp ld3
  sti state[816] = add1          cx add1 state sp ld3
  js_BoxInt32_1 = call #js_BoxInt32 ( cx add1 )
                                 cx add1 state sp ld3 js_BoxInt32_1
  ldq3 = ldq cx[296]             cx add1 state sp ld3 ldq3 js_BoxInt32_1
  sti ldq3[96] = js_BoxInt32_1
                                 cx add1 state sp ld3
  ldq4 = ldq cx[296]             cx add1 ldq4 state sp ld3
  ldq5 = ldq ldq4[120]           cx add1 ldq5 state sp ld3
  map = ldq ldq5[0]              cx add1 state map sp ld3
  add2 = add ld3, 1              add2 cx add1 state sp
  sti state[824] = add2          add2 cx add1 state sp
  ldq6 = ldq cx[296]             add2 add1 state ldq6 sp
  ldq7 = ldq ldq6[120]           add2 add1 state sp ldq7
  map = ldq ldq7[0]              add2 add1 state sp map
  sti sp[0] = add2               add2 add1 state sp
  sti sp[8] = 100                add2 add1 state
  sti state[816] = add1          add2 state
  sti state[824] = add2          state
  loop                           state

=== Translating LIR fragments into assembly:
=== -- Compile trunk 0000000000561FC0: begin
=== -- Compile trunk 0000000000561FC0: end

その後、ネイティブコードを生成。これもログを生成するように指定するので、

=== Aggregated assembly output: BEGIN
===
  000023ff29   [prologue]
  000023ff29    55
  000023ff2a    48 8b ec
  000023ff2d   [patch entry]
  000023ff2d    48 83 ec 30
  ## patching branch at 000023ffd6 to 000023ff31
  000023ff31:
  ## compiling trunk 0000000000561FC0
      state = iparam 0 rcx
      sp = ldq state[0]
      rp = ldq state[8]
      cx = ldq state[16]
      eos = ldq state[24]
      eor = ldq state[32]
      ld1 = ld cx[0]
      0
      eq2 = eq ld1, 0
      eq2 = eq ld1, 0
      xf2: xf eq2 -> pc=000000000049BEAB imacpc=0000000000000000 sp+0 rp+0
  000023ff31    48 89 4d f0           rcx(state)
  000023ff35    48 8b f1              rcx(state)
  000023ff38    48 8b 7e 00           rsi(state)
  000023ff3c    48 8b 4e 10           rsi(state) rdi(sp)
  000023ff40    8b 59 00              rcx(cx) rsi(state) rdi(sp)
  000023ff43    83 fb 00              rcx(cx) rbx(ld1) rsi(state) rdi(sp)
  000023ff46    0f 85 4d 00 02 00     rcx(cx) rsi(state) rdi(sp)
  ----------------------------------- ## BEGIN exit block (LIR_xt|LIR_xf)
  000025ff99:
  ## merging registers (intersect) with existing edge
  000025ff99    8b 4d f0
  000025ff9c    b8
  000025ffa1    48 8b e5
  000025ffa4    e9 32 00 fe ff
  ----------------------------------- ## END exit block 000000000054C8A8
      ld2 = ld state[816]
      $global0 = i2f ld2
      sti sp[0] = ld2
      ldq1 = ldq cx[296]
      ldq2 = ldq ldq1[120]
      map = ldq ldq2[0]
      ld3 = ld state[824]
      $global1 = i2f ld3
      sti sp[8] = ld3
      add1 = add ld2, ld3
      ov2 = ov add1
      ov2 = ov add1
      xt3: xt ov2 -> pc=000000000049BEB2 imacpc=0000000000000000 sp+16 rp+0
  000023ff4c    8b 96 30 03 00 00     rcx(cx) rsi(state) rdi(sp)
  000023ff52    89 57 00              rcx(cx) rdx(ld2) rsi(state) rdi(sp)
  000023ff55    8b 9e 38 03 00 00     rcx(cx) rdx(ld2) rsi(state) rdi(sp)
  000023ff5b    89 5f 08              rcx(cx) rdx(ld2) rbx(ld3) rsi(state) rdi(sp)
  000023ff5e    03 d3                 rcx(cx) rdx(ld2) rbx(ld3) rsi(state) rdi(sp)
  000023ff60    0f 80 43 00 02 00     rcx(cx) rdx(add1) rbx(ld3) rsi(state) rdi(sp)
  ----------------------------------- ## BEGIN exit block (LIR_xt|LIR_xf)
  000025ffa9:
  ## merging registers (intersect) with existing edge
  000025ffa9    8b 4d f0
  000025ffac    b8
  000025ffb1    48 8b e5
  000025ffb4    e9 22 00 fe ff
  ----------------------------------- ## END exit block 000000000054CA68
      i2f2 = i2f add1
      sti sp[0] = add1
      sti state[816] = add1
      js_BoxInt32_1 = call #js_BoxInt32 ( cx add1 )
      JSVAL_ERROR_COOKIE
      eq1 = eq js_BoxInt32_1, JSVAL_ERROR_COOKIE
      eq1 = eq js_BoxInt32_1, JSVAL_ERROR_COOKIE
      xt2: xt eq1 -> pc=000000000049BEB6 imacpc=0000000000000000 sp+8 rp+0
  000023ff66    89 57 00              rcx(cx) rdx(add1) rbx(ld3) rsi(state) rdi(sp)
  000023ff69    89 96 30 03 00 00     rcx(cx) rdx(add1) rbx(ld3) rsi(state) rdi(sp)
  000023ff6f    4c 8b e6              rcx(cx) rdx(add1) rbx(ld3) rsi(state) rdi(sp)
  000023ff72    48 8b f2              rcx(cx) rdx(add1) rbx(ld3) rdi(sp) r12(state)
  000023ff75    48 63 d2              rcx(cx) rbx(ld3) rsi(add1) rdi(sp) r12(state)
  000023ff78    4c 8b f1              rcx(cx) rbx(ld3) rsi(add1) rdi(sp) r12(state)
  000023ff7b    48 63 c9              rbx(ld3) rsi(add1) rdi(sp) r12(state) r14(cx)
  000023ff7e    48 b8                 rbx(ld3) rsi(add1) rdi(sp) r12(state) r14(cx)
  000023ff88    ff d0                 rbx(ld3) rsi(add1) rdi(sp) r12(state) r14(cx)
          000000000023FF8A:
  000023ff8a    49 8b cc              rbx(ld3) rsi(add1) rdi(sp) r12(state) r14(cx)
  000023ff8d    4c 8b e0              rax(js_BoxInt32_1) rcx(state) rbx(ld3) rsi(add1) rdi(sp) r14(cx)
  000023ff90    41 83 fc 10           rcx(state) rbx(ld3) rsi(add1) rdi(sp) r12(js_BoxInt32_1) r14(cx)
  000023ff94    0f 84 1f 00 02 00     rcx(state) rbx(ld3) rsi(add1) rdi(sp) r12(js_BoxInt32_1) r14(cx)
  ----------------------------------- ## BEGIN exit block (LIR_xt|LIR_xf)
  000025ffb9:
  000025ffb9    b8
  000025ffbe    48 8b e5
  000025ffc1    e9 15 00 fe ff
  ----------------------------------- ## END exit block 000000000054CBC8
      ldq3 = ldq cx[296]
      sti ldq3[96] = js_BoxInt32_1
      ldq4 = ldq cx[296]
      ldq5 = ldq ldq4[120]
      map = ldq ldq5[0]
      #3FF00000:0 /* 1 */
      1
      add2 = add ld3, 1
      ov1 = ov add2
      ov1 = ov add2
      xt1: xt ov1 -> pc=000000000049BEB7 imacpc=0000000000000000 sp+0 rp+0
  000023ff9a    4d 8b ae 28 01 00 00  rcx(state) rbx(ld3) rsi(add1) rdi(sp) r12(js_BoxInt32_1) r14(cx)
  000023ffa1    45 89 65 60           rcx(state) rbx(ld3) rsi(add1) rdi(sp) r12(js_BoxInt32_1) r13(ldq3)
  000023ffa5    83 c3 01              rcx(state) rbx(ld3) rsi(add1) rdi(sp)
  000023ffa8    0f 80 18 00 02 00     rcx(state) rbx(add2) rsi(add1) rdi(sp)
  ----------------------------------- ## BEGIN exit block (LIR_xt|LIR_xf)
  000025ffc6:
  000025ffc6    b8
  000025ffcb    48 8b e5
  000025ffce    e9 08 00 fe ff
  ----------------------------------- ## END exit block 000000000054CD50
      i2f1 = i2f add2
      sti state[824] = add2
      ldq6 = ldq cx[296]
      ldq7 = ldq ldq6[120]
      map = ldq ldq7[0]
      sti sp[0] = add2
      #40590000:0 /* 100 */
      100
      sti sp[8] = 100
      lt1 = lt add2, 100
      lt1 = lt add2, 100
      xf1: xf lt1 -> pc=000000000049BEC0 imacpc=0000000000000000 sp+16 rp+0
  000023ffae    89 99 38 03 00 00     rcx(state) rbx(add2) rsi(add1) rdi(sp)
  000023ffb4    89 5f 00              rcx(state) rbx(add2) rsi(add1) rdi(sp)
  000023ffb7    41 bc                 rcx(state) rbx(add2) rsi(add1) rdi(sp)
  000023ffbd    44 89 67 08           rcx(state) rbx(add2) rsi(add1) rdi(sp) r12(100)
  000023ffc1    83 fb 64              rcx(state) rbx(add2) rsi(add1)
  000023ffc4    0f 8d 09 00 02 00     rcx(state) rbx(add2) rsi(add1)
  ----------------------------------- ## BEGIN exit block (LIR_xt|LIR_xf)
  000025ffd3:
  000025ffd3    b8
  000025ffd8    48 8b e5
  000025ffdb    e9 fb ff fd ff
  ----------------------------------- ## END exit block 000000000054CF20
      sti state[816] = add1
      sti state[824] = add2
      1
      loop
  000023ffca    89 b1 30 03 00 00     rcx(state) rbx(add2) rsi(add1)
  000023ffd0    89 99 38 03 00 00     rcx(state) rbx(add2)
  000023ffd6    e9 00 00 00 00
  000023ffdb   [epilogue]
  000023ffdb    48 8b e5
  000023ffde    5d
                c3
===
=== Aggregated assembly output: END

===
=== END LIR::compile(000000000054A470, 0000000000561FC0)
===============================================================================

細かく出力条件を設定できるようになっているのは、いい感じ。

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